WTA VHDL shift left and shift right code different

[alpha91]

Hi, i have learned the shift register code in VHDL as the following:

---

Code VHDL - [expand]
1
2
3
4
if (reset = '1') then
shift <= '0000" ;
else if (clock' event and (clock= '1')) then
shift <= shift (2 downto 0) & si;

---

can anyone tell me this is shift left or shift right? because now i need VHDL for both shift left and shift right.

 

[SynthWorks]

Hi
shift <= shift (2 downto 0) & si;

This is shift left. Algorithm = remove left most element and add new element on right.

 

[alpha91]

This is shift left. Algorithm = remove left most element and add new element on right.

thanks for reply. what i need to do if i want to shift right?

 

[axcdd]

Remove right most element and add new element on left ?

shift <= si& shift (3 downto 1);

 

[alpha91]

Remove right most element and add new element on left ?

shift <= si& shift (3 downto 1);

i think you are right...