module gcd(clk, start, a_in, b_in, a_out, b_out, done);
input clk;
input start;
input [31:0] a_in;
input [31:0] b_in;
output reg [31:0] a_out = 0;
output reg [31:0] b_out = 0;
output reg done = 0;
reg [3:0] cnt = 0;
reg rst_in = 0;
reg rst_start;
integer a,b;
wire [31:0] result;
wire recv = 0;
always@(posedge clk) begin
if(start)begin
a <= a_in;
b <= b_in;
cnt = 1;
end
else if(b==0 || b==1) begin
a_out <= a;
b_out <= b;
done <= 1'b1;
cnt = 2;
end
else if(cnt == 1)begin
rst_in<= 1;
cnt = 2;
end
else if(recv == 1)begin
a <= b;
b <= mod_gcd.result;
a_out <= 1;
rst_in <= 0;
cnt = 1;
end
end
modulus mod_gcd(clk,start,rst_in,a,b,result,recv);
endmodule