h**p://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf
page 4
Verilog-2001 adds two new system functions,
$signed and $unsigned. These system functions are used
to convert an unsigned value to signed
Once you declare the variable as integer .it should be signed
verify with this code just modified Mrflibbbles code to illustrate the fact
no separate format specifier is needed %d is enough if you declared variable as integer .
Code:
module trb();
integer fp1;
integer i=32'h FFFFFFFF;
initial begin
fp1=$fopen("ctq.txt");
$fwrite(fp1,"Are we sure ... %d\n",i);
i=32'h 7FFF_FFFF;
$fwrite(fp1,"Are we sure ... %d\n",i);
$fclose(fp1);
end
endmodule
Are we sure ... -1
Are we sure ... 2147483647
In first fwrite i is having negative sign as the MSB is 1 ,so the particular number is the 2's complement of another number (-1) .
In second one i is having Msb 0 that means a postive number.