Writing test bench for my VHDL code?

[Jorge Jesse Cantu]

For my following code for a priority encoder, how would I write a test bench for this? I've seen several different examples for encoders and mux's but they all seem to differ and do not explain much. I would like someone to walk me through the process and maybe show me a test bench for my particular code.

Here is my VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity priorityencoder is
    port(en_l: in std_logic;                            --Active low enable
          din: in std_logic_vector(3 downto 0); --Active high data input
          dv_l: out std_logic;                          --Valid output active low
          dout: out std_logic_vector(1 downto 0)  --Active high data output
          );
          
end priorityencoder;
 
architecture Behavioral of priorityencoder is
signal en: std_logic;
signal dv: std_logic;
 
begin
en <= not en_l;     --Activation level conversion
dv_l <= not dv;     --Activation level conversion
 
process(din, en)
begin
    if(en = '1' and dv = '1') then
        if(din(0) = '1') then
            dout <= "11";           --LSB has priority
        if(din(1) = '1') then
            dout <= "10";
        if(din(2) = '1') then
            dout <= "01";
        if(din(3) = '1') then   --MSB has least priority
            dout <= "00";
        end if;
    elsif(en = '0') then
        dv <= '0';
        dout <= "00";       
    end if; 
end process;
end Behavioral;

 

[FvM]

As a first step, reconsider the implemented logic. dv is never activated, thus the design has no reasonable output.

The small priority encoder can be tested by applying all possible input signal combinations.