modelsim clock
hi wolfheart,
i found ur code seems to be error free,
i changed and added values of load and enable signals in test bench,
i got values at the output port "output",
ur code is abolutely error free when
simulated with modelsim,
ur try to add
the following values
"wait for 100 ns;
enable <= '1'; " in the process statment of the file shifter_tb.vhd,
and also change the value of "load" in procedure statment of the shift_package.vhd
file and it will definitley work,