write to a file at an event (verilog)

[spman]

Hi,
I have a problem with simulation.
I want to write the value of a signal into a file at positive edge of another signal. How should I use file commands to achieve it?

I wrote this code

	initial begin
		FileW = $fopen("dataout.txt", "w");
		forever begin
			if (Enable) begin
				#10;   //prevent writing frequently. clk is 10 ns
				$fwrite(FileW, "A=%d B=%d C=%d\n", A, B, C);
			end
		end
	end

But it doesn't work!

 

[TrickyDicky]

try this:

forever begin
  @ ( posedge clk )
    $fwrite(FileW, "A=%d B=%d C=%d\n", A, B, C);
end

 

[mrflibble]

Or for the short short version:

always @ ( posedge clk )
    $fwrite(FileW, "A=%d B=%d C=%d\n", A, B, C);

Anyways, check out the difference between putting it inside an "initial" block and outside it. As in, take your favorite verilog language reference and read the bit on "initial" block. That might help if I am guessing the thought process correctly.