Write leveling in DDR3 controller

[powerstar007]

ddr3 write leveling

Does any body know how the implementation from the controller side look like regarding write leveling? Does the controller need to generatae any enable signals to control the delay to be added to the DQS signals and if so, how does the controller how much delay it should add.

Thanks in advance!!

 

[kishore2k4]

write leveling

Does any body know how the implementation from the controller side look like regarding write leveling? Does the controller need to generatae any enable signals to control the delay to be added to the DQS signals and if so, how does the controller how much delay it should add.

Thanks in advance!!

I know very little about DDR3 standard.The controller has to delay the signals itself. You can find the delay values in the datasheets. All high-end FPGAs support this feature and you can take a look at their application notes.