I did figure it out by then actually! Thanks a lot mate! I really appreciate it!
The code I used:
Code:
process(clk)
variable counter: integer range 0 to 9 :=0;
begin
if rising_edge(clk) then
counter := counter + 1;
if counter = 9 then
Sig_A <= Sig_B;
end if;
end if;
end process;
I did figure it out by then actually! Thanks a lot mate! I really appreciate it!
The code I used:
Code:
process(clk)
variable counter: integer range 0 to 9 :=0;
begin
if rising_edge(clk) then
counter := counter + 1;
if counter = 9 then
Sig_A <= Sig_B;
end if;
end if;
end process;
But this code will not wait for 10 clocks. only 9 clocks though. Increase the range to 15 (since no one is going to question, as hardware will take even if you dont change) and counter to check for value 10. The problem is this is var, not sig. So '0' is not taken into account
it will be, just not on the first run-through.
actually what happens here is the counter is added and compared before a register. If you move the counter to below the comparitor it will work as you expect.
I said signal because I've some designers here advising me to use "signals" in place of "variables" and adjust the logic slightly. This is just to gain timing match for your circuit, because variables are little tough at timing predictions.
There is nothing wrong with variables, as long as you understand the hardware that will be created by the synthesisor.
The best advice is to stick with signals until you understand what you're doing.