write a code in verilog HDL BCD counter please i need help! :(

[emy jack]

hi all

can someone help me in this question

We would like to design a 2-decade up/down BCD counter in HDL language using behavioral
description. Since the counter is a 2-decade one, it is thus able to count from 00 to 99 and then
back to 00.
The counter has the following input control signals:
1. Load signal to load inputs in parallel.
2. Up signal so that the counter can count upwards.
3. Down signal so that the counter can count downwards
Note that the order of precedence for the 3 control signals defined above is Load, Up and Down.


:sad: Tomorrow I have to deliver the solution

 

[barry]

:sad: Tomorrow I have to deliver the solution

Well, I guess SOMEBODY needs to get to work.

Why don't you at least TRY something and then ask questions, rather than coming on here and expecting somebody else to do your homework.

 

[emy jack]

oh no !

i try many times and i just waste my time

please barry can you help me?

what you thik about this code


module cnt_bcddir ( dout4, dir, clk, arst, srst, en );
output [3:0] dout4;
input dir;
input clk, arst, srst, en;

// declaration of signals inside this block
reg [3:0] reg_cnt;
reg [3:0] nxt_cnt;

always @ ( posedge arst or posedge clk ) // dff_cnt
begin
if ((arst == 1'b1)) reg_cnt <= 1'h0;
else
if ((srst == 1'b1)) reg_cnt <= 1'h0;
else
if ((en == 1'b1)) reg_cnt <= nxt_cnt;
end
// end dff_cnt

always @ ( reg_cnt or dir ) // cmb_cnt
begin
if ((dir == 1'b0))
if ((reg_cnt == 9)) nxt_cnt <= 1'h0;
else nxt_cnt <= (reg_cnt + 1);
else
if ((reg_cnt == 0)) nxt_cnt <= 4'b1001;
else nxt_cnt <= (reg_cnt - 1);
end
// end cmb_cnt

// outputs --
assign {dout4}=reg_cnt;
//--
endmodule



:-(

- - - Updated - - -




:-(

 

[barry]

Okay, at least we know you tried. Unfortunately, I don't know Verilog, just VHDL. But I suspect the problem is in your second block (always@(reg_cnt)...)

If Verilog is like VHDL, then at least one of the elements in the sensitivity need to CHANGE in order for the process to run. (At least in simulation). There is nothing to guarantee that reg_cnt or dir change.

Somebody who knows verilog needs to answer this.

 

[ads_ee]

Firstly please use code or syntax tags next time you post code.

Why do you have both a arst and a srst? Use one or the other, I can't see any good reason to use both a sync and async reset on a register, it justs wastes resources.

I would rewrite the clocked always block to include the up/down counter logic instead of putting it into a separate combinatorial block.

I would structure it more like this:

---

Code Verilog - [expand]
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always @ (posedge arst or posedge clk) begin
  if ( arst ) begin
    // add something here
  end else if (option_1) begin
    // add something here
  end else if (option_2) begin
    // add something here
  end else if (option_3) begin
    // add something here
  end else begin
    // add something here
  end
end

---

I leave the details up to you.

 

[slava_edf]

I generate Verilog/VHDL/AHDL using Quartus II by 7 click mouse
https://project-ideas-yaroslav.blogspot.com/2012/01/verilog-code-counter-by-7-mouse-click.html