Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Working of SR latches

Status
Not open for further replies.
A

akki199421

Newbie level 1
Newbie level 1
Joined
Dec 9, 2012
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,287
I don't fully understand the working of sr latch....i have a prblm..consider a condition when S=0 and R=1 and Q=1 ,then what will be the output....and when S'=0,R'=1 and Q=0.

plz rply..
 

Can you please clear what do you mean by output.. ? if Q is not.
and another thing is with your conditions you flipped S and R which is not conventional and if we forget about Q for now then these are just NOR gated SR latch and NAND gated SR latch.. so it would help if you can share the source of your problem , or its just an hypothetical condition?
 

It might help to watch an interactive simulation of an SR flip flop in its simplest form.

The link below is to a SR flip-flop made from 2 transistors.

It will open the falstad.com/circuit website, load the schematic and run it on your computer. (Click Allow to load the Java applet.)

https://tinyurl.com/b9lu8rj

Click the two logic inputs at the bottom (momentary switches labeled 'set' and 'reset').

You can watch the outputs change state.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top