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I don't fully understand the working of sr latch....i have a prblm..consider a condition when S=0 and R=1 and Q=1 ,then what will be the output....and when S'=0,R'=1 and Q=0.
Can you please clear what do you mean by output.. ? if Q is not.
and another thing is with your conditions you flipped S and R which is not conventional and if we forget about Q for now then these are just NOR gated SR latch and NAND gated SR latch.. so it would help if you can share the source of your problem , or its just an hypothetical condition?
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