Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Working of column decoder in SRAM

Status
Not open for further replies.
V

VirtuosoDracula

Junior Member level 1
Junior Member level 1
Joined
Oct 2, 2011
Messages
17
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Visit site
Activity points
1,388
Hi Experts,

I would like to understand that how does column decoding and multiplexing takes place concurrently in an SRAM.
For, eg I have a 64Kx8 SRAM, how will I get 8 bit output since by putting address to row and column decoder I will only be able to get a single bit selected.

Request you all to help me understand it.

Thanks in advance,
VD
 

It varies by device type but basically you are right but there are 8 circuits in parallel sharing the same address, one with each bit in it and they are each connected to one of the data pins.

Brian.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top