ranayehya
Junior Member level 3
Hello
I work with synopsys for the first time and some issues I have in running the synthsis
Design 'gng' has '2' unresolved references UID-341
In design 'gng' , Input port'clk' drives wired logic LINT-6
Connot find the design 'gng_ctg' in the library 'Work'LBR-1
Unable to resolve reference 'gng_ctg' in 'gng' LINT-5
and lots of warnings like this
I know these only warnings but after that I have these errors in design setup step
../syn/output/gng.v ; Error Port connection failed VER-500
Verilog parser cannot parse the ../syn/output/gng.v MWNL-047
Current design is not defined UID-4
Any help ?
Thanks in advance
I work with synopsys for the first time and some issues I have in running the synthsis
Design 'gng' has '2' unresolved references UID-341
In design 'gng' , Input port'clk' drives wired logic LINT-6
Connot find the design 'gng_ctg' in the library 'Work'LBR-1
Unable to resolve reference 'gng_ctg' in 'gng' LINT-5
and lots of warnings like this
I know these only warnings but after that I have these errors in design setup step
../syn/output/gng.v ; Error Port connection failed VER-500
Verilog parser cannot parse the ../syn/output/gng.v MWNL-047
Current design is not defined UID-4
Any help ?
Thanks in advance