With the powerful features possessed by SystemVerilog , why were VMM, OVM e.t.c made?

[matrixofdynamism]

SystemVerilog possesses some very powerful features like assertion based testing and constrained random testing, not to mention OOP. I am sure that people can come up with various ways to create testbenches using all the tools available within SystemVerilog.

Why then have people developed things like VMM, OVM, UVM?

How would you describe UVM? I do know that it stands for universal verification methodology. Besides this it has now become the main industry standard having replaced all other ones like OVM, VMM e.t.c which have all become obsolete. I know that it provides instructions on a certain way to create the test environment when using SystemVerilog for verification. But why do we even need it to begin with?

 

[dave_59]

Because you need freedom from choice. The problem with any powerful language is that there are too many different ways to use them. You need methodologies based on standard Design Patterns to make the code more re-usable and interchangeable. The UVM standardizes the way you setup your testbench environment, run it, and figure out when to finish. And not only do you get re-usable code, you get re-usable people who understand the methodology that can move from project to project.