Ameera Q
Newbie level 3

Salam everyone,
I'm new to the forum, I'll try to explain my problem step by step:
In my verilog code I have one top module and one sub module that is generated many times using generate for loop, the output of one sub-module is an input to the next,
These I/Os is declared as array of wires in the top module and I'm passing for example wire as input and wire[i+1] as output. each wire is a vector of let us say N bits.
Inside the sub-module the input is converted to 2D array and used to produce a 2D array reg that is converted to a vector and assigned to the output.
my problem is that the value of OUT is updated but the value of W_OUT is not updated until the next CLK :sad:
W_OUT is a wire it should be updated immediately as far as I know. So why it isn't updated immediately ?? Is there something wrong with the assignment ??
Thanks in advance.
I'm new to the forum, I'll try to explain my problem step by step:
In my verilog code I have one top module and one sub module that is generated many times using generate for loop, the output of one sub-module is an input to the next,
These I/Os is declared as array of wires in the top module and I'm passing for example wire as input and wire[i+1] as output. each wire is a vector of let us say N bits.
Inside the sub-module the input is converted to 2D array and used to produce a 2D array reg that is converted to a vector and assigned to the output.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 //this is not my actual code but it is exactly what I'm doing module sub (CLK,E,W_IN,W_OUT); input CLK,E; input wire [N-1 : 0] W_IN; output wire[N-1 : 0] W_OUT; wire [W-1 : 0] IN [0 : N/W]; //2D array for input reg [W-1 : 0] OUT [0 : N/W]; //2D array for output //generate loop to convert from vector to 2D and vice versa genvar i; generate for (i= 0; i< N/W; i= i+1) begin :loop assign W_OUT [(i+1)*W-1 -: W] = OUT[i]; assign IN[i] = W_IN[(i+1)*W-1 -: W]; end endgenerate always @(posedge CLK or posedge E) begin // rest of code manipulates OUT
my problem is that the value of OUT is updated but the value of W_OUT is not updated until the next CLK :sad:
W_OUT is a wire it should be updated immediately as far as I know. So why it isn't updated immediately ?? Is there something wrong with the assignment ??
Thanks in advance.
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