willing to get any one expert

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Engr.KamranHameed

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Suppose I have designed a progarm let A verilog program like in C and assembly language and MatLab we can recall our function like "call" is used in assembly to recall a function can same type of logic be used in verilog if yes please send me simple verilog proagramme related to calling of function , mostly i have to use Case ,If and assign command but i am willing to know how function be called in verilog?
Thanks
 

https://www.asic-world.com/verilog/task_func1.html#Function

The following example was copied from the above site:
Example - Simple Function

1 module simple_function();
2
3 function myfunction;
4 input a, b, c, d;
5 begin
6 myfunction = ((a+b) + (c-d));
7 end
8 endfunction
9
10 endmodule

Example - Calling a Function

1 module function_calling(a, b, c, d, e, f);
2
3 input a, b, c, d, e ;
4 output f;
5 wire f;
6 `include "myfunction.v"
7
8 assign f = (myfunction (a,b,c,d)) ? e :0;
9
10 endmodule
 

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