will clock frequency for design change with inclusion of chipscope core

[syedshan]

hello all

chipscope core is introduced in my design only for debug purpose. later I wish to take it out...

But my question is that if I include chipscope core, there will be definitely timing differences, I suspect including chip scope

I intend to include more than 500 signals (collectively) to the chipscope core. The reason is that the design is quite large, involving DDR3 communication block + algorithm implementation + address generation....

Hence I am worried about the performance with and without chipscope...i.e. if I debug my design (which I find very useful actually...) using chipscope but later if removed and it work differenly bcz of timing changes....

thank you in advance

 

[TrickyDicky]

The clock speed you provide will be fixed. But the performance of the design will change with a chipscope core will change, probably negatively, as it now needs more resources and routing than before. But the key point is whether it still meets your timing requirements.

If you dont have full timing specifications, or lots of asynchronous nets, then yes, you probably will have problems, but these stem from poor design practice rather than the chipscope core.