Width of rising edge or falling edge of FF in FPGA?

[bravoegg]

I want to know the width of a rising edge or a falling edge, like how long do they last, is it a few ps or a few ns?
I couldn't google that out and I've tried some datasheet but still failed to locate the answer...

Could you guys show me where I can find the related information in the datasheet or manual or UG, altera or xilinx. Both will do.

Thanks.

Sy.

 

[ads-ee]

It's not defined in the documentation, but it is accounted for in the timing models used by the tools for place and route. It's also not going to be anywhere near ns duration, more along the lines of 10's of ps range.

Is there a specific reason for needing to know this information? It's not very useful IMO for doing any kind of FPGA design. Whatever the value is you can't do anything about it unlike say the I/O where you can change drive strength or use fast/slow.

 

[FvM]

FPGA datasheets have rise time specifications for input and output signals. Input signals, if not feed through ST buffers must have rise and fall times below a certain limit. Output signal rise time is varying according to used IO standard and output buffer configuration.

The timing of internal signals is ruled by parameters like maximum core clock rate, minimal signal pulse width and particularly setup and hold time of core FFs. They fully describe the expectable behavior of the FPGA logic core, you don't actually care for internal rise times.

 

[bravoegg]

It's concerning a project that generates a different widths of PWM waves to represent a train of codes. Now it comes to me that it is actually irrelevant since the rising and falling edge are at a level of 10's ps...

 

[bravoegg]

it's interesting detail. I've used FPGA more like a software and never went deep in the manuals...it's really bad for my job.

 

[FvM]

It's concerning a project that generates a different widths of PWM waves to represent a train of codes. Now it comes to me that it is actually irrelevant since the rising and falling edge are at a level of 10's ps...

Presumed your pwm is generated by synchronous logic, pulse widths are integer multiples of a clock period. It's accuracy is mainly limited by jitter and asymmetrical propagation delay of output buffers.

 

[bravoegg]

If I choose to pack output PWM register into IOB, will the performance be any better?

INST <register_instance_name> IOB = TRUE|FALSE

 

[FvM]

It could slightly reduce output jitter. The major advantage of output registers is to get lower skew between multiple output signals or output signals and clocks which is probably irrelevant for your application. But it surely does no harm.

A possible option is using double data rate registers to increase the pwm resolution with a given clock frequency.