Width mismatch error in VHDL..!!!

[talhaelex]

Hello Everyone !!
i have a small query in vhdl , i just want to write a code for de_mux for that i ave written the following entity and structural architecture component.
but at the time of compilation it is giving me error "Width mismatch. Expected width 6, Actual width is 3 for dimension 1 of t.
Expected width 3, Actual width is 6 for dimension 1 of b4 ."
can anyone please resolve this..??

port (A,B,C,D,E:in std_logic_vector(5 downto 0);
t:in std_logic_vector(2 downto 0);
b1,b2,b3,b4,b5ut std_logic_vector(5 downto 0));

u2: de_mux port map (t,y,b1,b2,b3,b4,b5);

 

[dillikumar406]

for demux you shoud have one input and many output. but in your code you defined many inputs

 

[electroM]

Post full code. by just observing U2 port map no one is able to help.