wide range high speed common mode level shifter

[sainiparvesh]

Hello All,
Can anybody suggest some closed loop architecture to level the 500MHz from 0.5-0.65V input common mode to 0.4V-1.3V output common mode. I tried (super)source follower based with dual SSF, first being pmos input and second being nmos input at 2.5V but I couldn't meet the linearity spec(>18dBm OIP3 with -7dBm input power). So now I am looking for some op-amp based level shifter for above spec.. It would great if anybody can suggest some reference or circuit etc.
Regards,
Pravesh

 

[FvM]

Can anybody suggest some closed loop architecture to level the 500MHz from 0.5-0.65V input common mode to 0.4V-1.3V output common mode.

Rather unclear. Are you talking about an amplifier? If so, which gain? Otherwise the input CM falls already in the output CM range, so no level shift required.

 

[sainiparvesh]

Rather unclear. Are you talking about an amplifier? If so, which gain? Otherwise the input CM falls already in the output CM range, so no level shift required.

Sorry for confusion. 1. Its an unity gain level shifter/buffer, Actually ADC(undecided) to be driven by this level shifter can be 1.1V or 2.5V, so actual range of interest for output CM is ~0.4-0.6V(1.1V ADC) and ~1.1-1.3V(for 2.5V ADC). Thatswhy I wanna design a LS to fulfill above range irrespective of ADC to be selected.

 

[FvM]

True differential amplifiers are the usual means to drive ADC with defined common mode voltage and increase common mode rejection at the same time.