Hi dftrl,
Setup timing analysis is done at the stage of placement because at the stage of placement if there is any setup violations then it is fixed only by making changes on data path(like inserting buffers,using LVT cells,cell upsizing) but we don't touch the clock path and at this stage clock is not propagated so,skew and insertion delay doesn't come into exsistance.So,set up is fixed at the stage of placement and hold is fixed after the CTS as clock is being propogated,Skew and insertion delay come into exsistance after CTS...,