why tri-state logic cannot be buffered

[rogeret]

In the book Advanced ASIC Chip Synthesis Edition 2 ( Chapter 5.4.4), it is said that Tri-state logic is difficult to optimize – since it cannot be buffered.
This can lead to max_fanout violations and heavily loaded nets.

Could Anyone explain it further why it cannot be buffered?

Thx!

 

[yx.yang]

Actually, there shouldn't exit any tri-state (nor bi-direction) logic within a digital chip, if you're using cell base design. Tri-state logic can just exit on IO PAD. For tri-state logic within a chip, there will be many headache. And Tri-state logic within a chip can be easily replace by two one-direction logic.
The headache maybe: multi-drive of the same wire, un-drive of the wire, causing metastable of the gates afer that wire. Then may casuing thermo problem because of the un-driven of logic cell input pins.

 

[rogeret]

Maybe its right, because when i use FPGA I cannot see any tri-state except on PAD.
Could u give me some materials about the headache caused by it? I want to know where and why to or not to use it in detail.

 

[yx.yang]

Sorry I don't have any meterial on hand. You can search in the internet.
Thanks.

 

[faizalism]

There is situation when few drivers want to access a bus. So, when 1 driver accessed, the rest of the driver need to be high-z.

 

[rogeret]

so, what is the problem?

 

[faizalism]

So, when 1 driver accessed, the rest of the driver need to be high-z.

If you have buffer in btwn driver and bus, can you make sure it is high-z?