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Hi,
In linear region, Id is very much dependent on Vds. So, even a small variation in vds(lets assume comes from poor mismatch), can change the curr a lot, which needs to be avoided.
In ohomic region a even a slight mismatch can make a drastic change in the output current can even change the operating region of Transistor. This is why if the two transistor to be matched you need to lay them with good matching.
The effect of the mismatch is not in any way magnified by using the MOS in linear mode!
If the MOS resistance is mismatched between two devices the relative current difference or relative voltage difference is equal and related to the MOS resistance mismatch.
MOS resistance mismatch is in typical circuit applications better than current mismatch because the Vdsat used is higher. That is because in resistor application you try to use a Vdsat much higher than the maximum voltage across the resistor to lower the resistor nonlinearity. In current source or amplification applications you try to make Vdsat low to get more voltage headroom. Mismatch is dominated by the threshold voltage mismatch and the channel mobility mismatch. If the Vdsat is low the threshold voltage mismatch dominates. Secondly channel length modulation is also a mismatched but does not impact the lienar mode.
So practically MOS resistors match better than MOS current sources.
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