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Why to use HVL (is HDL not enough?)?

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Advanced Member level 2
Nov 7, 2001
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Why HVL ?

I havent used any HVLs like Vera or E or System verilog. but i dont understand. Why should we use it. what is the advantage of using it over HDLs for doing functional verification.

Anyway once functionally verified we need to synthesize the design. So if we write it in HDL we can also synthesize it. Rather than writing one model for verification and another for synthesis.

Please help me.



The purpose of Hardware Verification Language(HVL) is
to solve the bottlebeck of the IC design flow: verification issue !

HDL(Hardware Description Language), such as Verilog or VHDL,
have made great success in the RTL design domain.
But as increasingly complexity of the ASIC design,
it seems that the original HDL could not meet the requirements.

HVL usually can model the device and environment in a higer level
than HDL. This capability let the prototype can be built earlier.
Sometimes, it will also provide some pre-defined device/bus models.

HVL usually has the assertion-based verification ability.
This feature can not only let you find the bug in the design
more quickly but also define a executable spec.

HVL usually supports the transaction-based verifiaction.
So, it can verify the design more efficient.

EDA tool venders, C@dence, for example, has already introduced
the unified verification environment.
So, I think that HDL and HVL would work together smoothly
in the near future.

The only problem is which HVL will be used in the unified environment ?

verification is the biggest challenge for successful SoC

Joe2moon has articulated the needs for HVL. I just want to add a few data points.

I happen to have participated in a few SoC designs, ranging from 3 million gates to 8 millions gates. Verification was the biggest challeng we faced. It usually takes us a year to do the design, and at lease another year to do the verification/bug fixes. We simply couldn't afford to make any mistake. The mask costs too much money, usually > 1 million $. If an SoC has to be re-spun a few times, the company is broke! Therefore it makes a lot of sense to put emphasis on verification.

Also, these days not all the IPs are developed in house. It's common to purchase 3rd party's IP. How are gonna make sure you bought something working? Rigorous verification.

HVL brings in completely new verification methodology. HVL is aimed to improve verification efficiency, improve coverage. With VHDL, it takes quite some effort to achieve what HVL can offer. With Verilog, forget it, the language itself is so limited. There is no way to achieve in Verilog what HVL offers.


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