Oct 11, 2015 #1 J JKR1 Junior Member level 3 Joined Aug 24, 2015 Messages 29 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 208 hi why this error happen?
Oct 11, 2015 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 This code describes a dual edge flip flop which cannot be done inside an fpga
Oct 12, 2015 #3 imbichie Full Member level 6 Joined Jul 30, 2010 Messages 381 Helped 55 Reputation 110 Reaction score 54 Trophy points 1,308 Location Cochin/ Kerala/ India or Bangalore/ Karnataka/ Ind Activity points 3,580 "wait" statement cannot be synthesis ...
Oct 12, 2015 #4 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 imbichie said: "wait" statement cannot be synthesis ... Click to expand... Yes it can, but its not the recommended style. The following will synthesise to a register: Code VHDL - [expand]1 2 3 4 5 process begin wait until rising_edge(clk) q <= d; end process;
imbichie said: "wait" statement cannot be synthesis ... Click to expand... Yes it can, but its not the recommended style. The following will synthesise to a register: Code VHDL - [expand]1 2 3 4 5 process begin wait until rising_edge(clk) q <= d; end process;