I just used a standard two-stage OP (p-input pairs).
Hi leo
while reducing the number of poles and zeros is definitely the way to go, notice that here the biggest problem here is actually the presence of 2 complex conjugate zeros that create that 'notch' feature in the loop gain, even when we reduce the opamp to a single stage I am not sure that will go away.
I am not sure what creates them (it is basically a gyrated cap somewhere) but adjusting the relative bandwidth of the 3 amplifiers (OPb and the 2 common source amps in the feedback loops) might be key.
One way out of this is too add 2 poles on top of the zeros but it would be nice to understand if there is a more elegant (and practical) way to fix this
Please, tell us about your "standard two-stage OP".
Did you create your own model? Is it a manufacturer model? Which type?
Which parameters: open-loop gain, input/output impedances?
In particular, the output impedance seems to be "critical". Otherwise I have no explanation for the output voltage that shows NO continuous reduction for rising frequencies (as shown in one of the earlier diagrams).
I used a real transistors for that OP. The DC gain is around 40dB.
Below are the impedance:
v(vo)/v+ = 86.3035
input resistance at v+ = 1.000e+20
output resistance at v(vo) = 140.5832k
allennlowaton,
I do not understand these data.
Does this mean that your "opamp model" consists of one transistor only? Please clarify.
Then I repeat my question:
What are the main parameters of your "opamp" model: gain, input and output resistance?
OK, now I got it.
You are using an amplifier model with a dc gain of 40 dB and an output resistance of 140 kohms, right?
If this really is the case, I am not surprised about weird simulation results.
The circuitry in your original drawing (posting #1) contains opamps - and I doubt if the models you are going to use can be called "opamp".
At first, you have a gain of only 40 dB (rather than 80...100 dB for classical opamps).
And secondly, a large output resistance of 150 kohms is connected to a gate node of a FET that has an input resistance app. in the same order. In fact, you have a voltage controlled current source, but not an opamp model. I am afraid, that this cannot work as required.
PS: This also explains why the output voltage of your "opamp model" does not decrease down to zero for rising frequencies.
PS2: This also explains the big differences between ideal and "real" amplifier results as reported in posting #5
(ideal: zero output resistance; real: 140 kohms)
a large output resistance of 150 kohms is connected to a gate node of a FET that has an input resistance app. in the same order"??? what kind of FETs are you referring to? in .18um tech gate leakage is completely negligible
Completely? Independent on frequency? I didn't speak of "leakage" but of the normal load (however, I agree, I should have used the term "impedance" instead of "resistance").
While the name opamp is usually reserved for differential amplifiers capable of driving resistive loads, what he is using -an OTA- is perfectly adequate in the current situation where he is driving purely capacitive loads (a little more gain would not hurt but still)
Does this mean that in the circuit under discussion the opamps (I suppose the used symbols designate voltage output amplifiers) can be replaced by OTA's without influence on the principal function?
If I remember well, it was earlier reported that everything was OK with ideal opamps (with voltage output!).
Or am I wrong?
https://www.edaboard.com/members/256716/
of course it helps, in a system with the same number of poles and zeros you need to fix the behavior at high frequency first, a large cap somewhere has to push it below 0dBHi allennlowaton,
may I give a general comment? For my opinion, there is to much "trial and error" on your side.
Of course, the "gain" goes down due to a capacitor at the amplifier output (I avoid the term "opamp"), and with 100 pF it will be even lower, but - does this really help?
Man you should be paying attention to your own posts because the loop gain is done (correctly) with an inline probe inserted on the output wire (see your post #47)By the way: In your own interest, be exact to avoid misunderstandings and irrelevant answers. I suppose with "gain" you mean "loop gain", don't you? (Such a circuit has several different "gains"). Are you sure to simulate the loop gain correctly?
interesting: how are a low output resistance amplifier and an amplifier capable of driving resistive loads (w/o losing gain) any different?To do a systematic approach I recommend the following:
* Where does the whole circuit originate from? Are the shown amplifier symbols in the original circuit opamps or OTA's?
I didn't design such a circuit up to now, therefore my question.
* With "opamp" I mean VCVS . Somebody in the forum is of the opinion an opamp would be a diff. amplifier "capable to drive resistive loads". I think this does not meet the point and is not true (think of active filter applications with capacitive load impedances). To me, an opamp is a high gain amplifier with negligible output resistance. An output resistance of 100 kohms and more belongs - more or less - to a VCCS (OTA with a different symbol as shown!).
he already told you he is using real transistors not a model in his simulations* Therefore, try to equip your amplifier model with a low output resistor (at first: ideal buffer) - just to see if this shows good results with a loop gain that crosses the 0 dB line and goes down. And check again the dc bias points.
(As I have asked already in my last posting: Didn't you simulate already with ideal opamps and with success?)
* Then, if the circuit tends to be unstable you/we can think about stabilization methods.
* I am afraid, without some systematic steps you will have no success.
Good luck, regards
LvW
Oh, I forgot to mention another important point:
The methods discussed to simulate the loop gain (L-C method and ac source in series with the amplifier output) are applicable to opamps with low output resistances only!
That means, all loop gain results you have shown up to now exhibit large errors because the load is disconnected from the amplifier output (and the large output resistance).
This is a good example that lack of information (output resistance) leads to severe misinterpretations and false answers. If the output resistance plays a role, the more complicated method to simulate the loop gain as proposed by Middlebrook and others is to be applied.
Same here, hopefully we'll all learn something out of thisHi dgnani,
I can't resist to reply again:
this is why we use compensationLoad impedance of the same magnitude as the amplifier output resistance simply means you are looking at a frequency beyond your amplifier bandwidth namely at its -6dB point... this will happen somewhere no matter the output resistance and does not make a difference for this application: it will still work at DC, right?
Up to now I was of the opinion we are discussing stability matters. And you certainly know that an unstable circuit is unstable - independent on the operating frequency. Example: Each student knows (hopefully!) that an uncompensated opamp with 100% feedback is unstable - even if it will be used at dc only.
Just by quickly looking on my desk:The only difference between an OTA and an opamp is their output resistance, never seen anybody using a different symbol for it, when you are driving a capacitive load in a DC application you just get a different frequency response
Regarding the OTA symbol: I know a lot of english textbooks dealing with opamps and OTA's. I can't remember a single one that uses the opamp symbol (triangle) for OTA's also.
The following link leads you to one of the earliest and classical publication for OTA applications. I am really surprised that you never have seen the OTA symbol that was used since then in nearly all OTA publications.
**broken link removed**
what gain reduction? we are simply changing the behavior above the largest pole and zero not the DC gain, which is all we need to operate this circuit (once it is compensated)of course it helps, in a system with the same number of poles and zeros you need to fix the behavior at high frequency first, a large cap somewhere has to push it below 0dB
In control theory I have learned that this "method" (pure lag compensation) stabilizes a loop "until it is dead".
Of course, you always can reduce the gain until the circuit is stable. But - if the circuit works as required after all?
A very robust method. Therefore my former question: Does it help to solve the problem?
we must be reading from different Middlebrooks' **broken link removed**Middlebrook method to measure loop gain uses a single injection probe w/o any input signal nor zeroing, how is this different than what he is already doing?
I recommend to read about Middlebrooks method again. He uses not a single injection probe, but two injection sources in two simulation runs. For your understanding: The second run with a current source is necessary in order to correct the error that was introduced by the first run with a voltage source.
And what is the cause of this error? The finite output resistance of the amplifier! Therfore, for opamp (VCVS) applications one can save this second run; for amplifier with higher output resistances it is an absolute "must".
Thank you
LvW
A final word to allannlowaton:
I hope you are not confused about this discussion. I still recommend to follow all the steps as contained in my posting #72.
Hi LvWQuote pancho_hideboo: we must be reading from different Middlebrooks' try this, page 8
Nope it nor clear not obvious even more so because that paper does not mention anything about what's best for large output resistances andI know all the Middlebrook publications, however, for our limited purpose (loop gain only) the GFT manual referenced by you is not the best as it deals with the implementation of the GFT (for other readers: general feedback theorem) into the ICAP simulator. More than that, the GFT can do much more than to simulate the loop gain only.
Nevertheless, of course our problem of loop gain calculation is covered also in this document. But not on page 8, instead
you should read pages 10 pp. Why? Because up to page 10 Middlebrook deals with block diagrams only without interaction (finite input/output impedances). Starting with page 11 (chapter 3) he now considers block interaction as is the case in our circuit under discussion. For clarification, I like to give an excerpt from pages 10,12 (introduction to chapter 3):
Quote Middlebrook (page 10):
The next step is to relate the block diagram of Fig. 3 or 4 to an actual equivalent circuit
model of the system under consideration. This is where difficulties begin to emerge: the conventional
approach attempts to identify the three blocks as containing distinct parts of the circuit, but this is
only true in simple cases. Usually interactions between blocks (loading) impose approximations
page 12:
In the previous section, it was shown how the four second level TFs could in principle be
evaluated by injection of a test signal uz into the block diagram. The difficulties arise when we try
to implement these calculations on the actual circuit diagram instead of on the block diagram. In
particular, is uz a current or a voltage source?
The answer is that, in general, uz is both a current and a voltage source ......
I hope it is clear and obvious now that all amplifiers (assuming uni-directional operation according to Middlebrook) that have a relatively large output resistance require a voltage and a current injection for loop gain calculation.
_______________
dgnani, one last question: In my reply #72 I did nothing else than to help allennlowaton a little by recommending a systematic approach in designing the circuit resp. in finding some error sources. Why do you argue against this ?
I cannot understand.
________________
Regards
LvW
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?