sapphire
Member level 3
Hi,
This is a famous PLL paper, and I just went back to check it out. I understand that the replica bias is used to dynamically adjust the bias current in accordance with supply variation. Therefore, the lower swing limit of the buffer stage is always equal to Vctrl. This is good. But the output resistance of the symmetrical load is still related to the supply voltage. So the delay is still affected by the Vdd to the first order. Why he claims it's low jitter and supply insensitive buffer?
The paper is called "low-jitter process-independent DLL and PLL Based on Self-Biased Techniques"
Thanks
Sapphire
This is a famous PLL paper, and I just went back to check it out. I understand that the replica bias is used to dynamically adjust the bias current in accordance with supply variation. Therefore, the lower swing limit of the buffer stage is always equal to Vctrl. This is good. But the output resistance of the symmetrical load is still related to the supply voltage. So the delay is still affected by the Vdd to the first order. Why he claims it's low jitter and supply insensitive buffer?
The paper is called "low-jitter process-independent DLL and PLL Based on Self-Biased Techniques"
Thanks
Sapphire