Why state machine is not triggered?

[EDA_hg81]

I am implementing FSM inside Altera FPGA.

I have set the initial FSM = idle.

Why FSM is not triggered?

How the FSM is stuck?

Thanks.

process ( clkin ) 
		begin
			if (rising_edge(clkin)) then
				vsyndet0 <= v_sync;
				vsyndet1 <= vsyndet0;
				vsyndet2 <= vsyndet1;
				vsyndet3 <= vsyndet2;
			end if;   
		end process;

process ( clkin )  
        begin
             if (falling_edge(clkin)) then
	case state is
                      when idle    =>
	           if ( vsyndet3 = '0'       and vsyndet2 = '0' and vsyndet1 = '1' and vsyndet0 = '1') then
		          state <= vsyncrdet;
                     end if;

 

[manish12]

give full code text>>

 

[oursriharsha]

please add a reset condition , and a reset signal in the proceess where in the FSM will go in to the state of initialization.

FSM initially should know which state it has to go ..


so please introduce a condition of reset and move to init state and let your rest of the states be linked as usual.



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Correct me if i am wrong!