why signal didnt get its value?

[fahim1]

hi
heres my code and i defined signal "inp" but its initial value depends on input and in simulation it didnt get its value,i defined it in another process as u can see its now commented but it still didnt work

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
entity serialm is
port(a,b : in std_logic_vector(3 downto 0);
  clk : in std_logic;
  out3 : out std_logic_vector(7 downto 0));
end serialm;
architecture serialm_arch of serialm is
  signal sum : std_logic_vector(2 downto 0) := "000";
  signal count :integer := 0;
  signal outtemp : std_logic_vector(7 downto 0) := "00000000";
  signal s1,s2,carry1,carry2,carry3,ena: std_logic := '0';
  signal inp :std_logic_vector(7 downto 0) := b(3 downto 0) & "0000";
  begin
    --process(a,b)
    --begin
      --if (clk ='1' and clk'event) then 
     --inp <= b(3 downto 0) & "0000";
     --ena <='1';
   --end if;
   --end process;
    process(clk)
    variable sum0,sum1,sum2,sum3 : std_logic := '0';
    variable c0,c1,c2,c3 : std_logic := '0' ;
    variable temp0,temp1,temp2,temp3 : std_logic_vector(1 downto 0) :="00";
    --variable inp :std_logic_vector(7 downto 0) 
    --inp := b(3 downto 0) & "0000";
    begin
      --if (ena ='1') then
      if (clk='1' and clk'event) then 
        if (count <9) then
        temp0(0) := ( a(0) and inp(3) )xor c0 ;
        temp0(1) := ( a(0) and inp(3) )and c0 ;
        sum0  := temp0(0);
        c0 := temp0(1);
        temp1(0) := (a(1) and inp(2))xor c1 ;
        temp1(1) := (a(1) and inp(2))and c1 ;
        sum1  := temp1(0);
        c1 := temp1(1);
        temp2(0) := (a(2) and inp(1))xor c2 ;
        temp2(1) := (a(2) and inp(1))and c2 ;
        sum2  := temp2(0);
        c2 := temp2(1);
        temp3(0) := (a(3) and inp(0))xor c3 ;
        temp3(1) := (a(3) and inp(0))and c3 ;
        sum3  := temp3(0);
        c3 := temp3(1);
        s1 <= sum0 xor sum1;
        carry1 <= sum0 and sum1;
        s2 <= sum2 xor sum3;
        carry2 <= sum2 and sum3;
        sum(0) <= s1 xor s2;
        carry3 <= s1 and s2;
        sum(1) <= carry1 xor carry2 xor carry3;
        sum(2) <= ((carry1 or carry2) and carry3) or (carry1 and carry2);
        outtemp(count ) <= sum(0);
        count <= count +1 ;
        inp <= '0'& inp(7 downto 1);
      elsif (count = 9 ) then 
      out3 <= outtemp(7 downto 0);
     -- ena <= '0';
      end if;
      end if;
    --end if;
    end process;
  end serialm_arch;

 

[TrickyDicky]

It is getting a value - its getting '0' shifted in. You havent run the simulation for enough clock cycles.

 

[fahim1]

It is getting a value - its getting '0' shifted in. You havent run the simulation for enough clock cycles.

i run it more but nothing happened,as u van see it have values UUUU.it shouldnt be U,it should be the value of b instead of U. how can i fix it?

 

[FvM]

I presume, you are writing VHDL for hardware design. In so far you should ask which hardware is intended with your HDL constructs and if the simulation will be consistent with expectable hardware behaviour. You have e.g. these initializers:

  signal outtemp : std_logic_vector(7 downto 0) := "00000000";
  signal s1,s2,carry1,carry2,carry3,ena: std_logic := '0';
  signal inp :std_logic_vector(7 downto 0) := b(3 downto 0) & "0000";

The first two lines will be implemented as power on reset which most FPGA tools. The outtemp waveform shows that Modelsim handles the initialitzer. But the non-constant initializer for inp doesn't represent synthesizable hardware and is apparently also ignored by Modelsim.

Although constant initializers are usually synthesizable, it's often preferable to implement an explicite reset signal and synchronous or asynchronous conditional assignments describing the reset action. One reason is that power on state is only set once, and the intended reset state may be dwarted by an undefined clock startup.

I'm sure you could avoid many of the issues presented in your recent threads by following the design templates in VHDL text books and tutorials.

 

[fahim1]

I presume, you are writing VHDL for hardware design. In so far you should ask which hardware is intended with your HDL constructs and if the simulation will be consistent with expectable hardware behaviour. You have e.g. these initializers:

  signal outtemp : std_logic_vector(7 downto 0) := "00000000";
  signal s1,s2,carry1,carry2,carry3,ena: std_logic := '0';
  signal inp :std_logic_vector(7 downto 0) := b(3 downto 0) & "0000";

The first two lines will be implemented as power on reset which most FPGA tools. The outtemp waveform shows that Modelsim handles the initialitzer. But the non-constant initializer for inp doesn't represent synthesizable hardware and is apparently also ignored by Modelsim.

Although constant initializers are usually synthesizable, it's often preferable to implement an explicite reset signal and synchronous or asynchronous conditional assignments describing the reset action. One reason is that power on state is only set once, and the intended reset state may be dwarted by an undefined clock startup.

I'm sure you could avoid many of the issues presented in your recent threads by following the design templates in VHDL text books and tutorials.

thanks for answering...
i didnt get this part,will u please explain it more

Although constant initializers are usually synthesizable, it's often preferable to implement an explicite reset signal and synchronous or asynchronous conditional assignments describing the reset action. One reason is that power on state is only set once, and the intended reset state may be dwarted by an undefined clock startup.

 

[FvM]

I guess you've already seen designs with explicite reset code, either asynchronous

---

Code VHDL - [expand]
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if reset = '1 then
  count <= 0;
  inp <= b(3 downto 0) & "0000";
elsif rising_edge(clk) then
  count <= count +1 ;
  --
end if;

---

or synchronous

---

Code VHDL - [expand]
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if rising_edge(clk) then
  if reset = '1 then
    count <= 0;
    inp <= b(3 downto 0) & "0000";
  else
    count <= count +1 ;
    --
  end if;
end if;

---