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Hi mujtaba ...
as u see set is the min time required by the data tobe stable before the clock transition and so the worst case would be only if you consider the max operating conditions for your std cells ....i.e., the PVT conditions as SS 1.98V (max) 125°C
so u use the Command.
setOpCond -max MAX -min MIN -maxlibrary slowlibrary -minlibrary fastlibrary
similarly the other way for the hold
we use the fast operating conditions to apply for the timing info for the cells.
setup violation occures when the delay of the logic between two FFs (having the same clock) is so large that the logic output is not ready on the input of the second FF before the next clock transition and this FF may sample the past value instead of sampling the current one. So if there is no delay there will be no fear of setup violations , which means that the setup violation is determined by the case of maximim delay.
On the other hand, Hold violation occurs when the delay of the logic between two registers (having the same clock) is so small that the second FF may sample the future value rather than sampling the current one . Thus hold time violations are more likely to occure when the logic delay is minimum.