Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why pulsed drain current is higher than continuous drain current in MOSFETs

Status
Not open for further replies.

hioyo

Advanced Member level 4
Joined
Aug 18, 2021
Messages
116
Helped
0
Reputation
0
Reaction score
2
Trophy points
18
Activity points
899
Why is pulsed drain current higher than continuous drain current in MOSFETs?
In MOSFET data-sheets, pulsed drain current is much higher than (by 4x) continuous drain current.
What is the reason behind thi
 


Many reliability (limiting) mechanisms behave the same whether you look at steady state or time averaged current / power. Averaging a pulse train "ratios down" the peak to a lesser number. You should also see a declaration about what duty cycle this limit is coupled to. You might see 10% or a fixed PW and freq and be left to do your own figuring regarding actual stress.

If you get 4X relief for 10X sandbagging, that's not much of a deal.
 

At the end, it's all about the heat. A continuous current will generate a temperature converging to a stable value after a short time. With a pulsed current, on the other hand. The smaller the duty cycle, due to the thermal gradient in that section of the chip, the greater the instantaneous ability of this heat to propagate in the silicon die, whose mass acts as a buffer for thermal transients. Think of an incandescent light bulb as an analogy; the filament takes time to radiate the light and goes out, it does not happen instantly.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top