Hi eng han,
Hi i agree with you that NMOS channel resisstance is less compared to PMOS
but to be act as a DE-CAP one would be tying source,drain and bulk together to VSS and gate to VDD in that aspect the resistance exist between source and drain must be like a shorted so no need to consider it .please feel free to correct me if i am wrong fron this DE-CAP perspective.
probably what you may pointing is the substrate resistance btween gate to substrate terminals stood as series resistance
hi jcpu,
i have few words on your comment if i am going to use PMOS as cap definitely gate is one terminal(given to VSS along with substrate(p-type) connected) and source ,drain and NWELL are tied to VDD
so it definitely operate in inversion region am i wrong?
apart from theory i have done some simulations in SPICE on this and found results bit confusing
.PRINT all(C)
when i used above statement to print all junction capacitances i found Cgs always be at 0 and Cbd=Cbs =total capacitance between terminals X(gate) (swept from
-VCC to 2*VCC) and Y(source,drain,bulk shorted together) (always tied to VSS)
Cgd is varying according to region of operation , Cds always has neglegible value
Any suggestins would be appreciable on this
From the PMOS point of view cap is formed between terminal X( gate and P-substrate tied to VSS ) terminal Y( source, drain and NWELL connected together given to VCC) when i did simulation i found 10X more cap than an normal NMOS realized cap , i was wondering what is the concept behind this to happen.
Regards
Kiran