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Why PMOS is not used as CAP

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kumar123

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Hi ,

Can anyone has an idea why PMOS canot be used as a CAP?
when i did rough simulation taking PMOS and NMOS of same L and Wp= 2*Wn i found that PMOS is giving more CAP value say if NMOS has value 0.13f the PMOS is having 2f

could anybody give idea on this why NMOS and NMOS in NWELL caps are good to use as D-CAPs

apart from this it would be much appreciable if anybody provide or point me docs on NMOS in NWELL how it gives better cap w.r.t to NMOS cap ?


Thanks for your support

Kumar
 

renwl

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kumar123 said:
Hi ,

Can anyone has an idea why PMOS canot be used as a CAP?
when i did rough simulation taking PMOS and NMOS of same L and Wp= 2*Wn i found that PMOS is giving more CAP value say if NMOS has value 0.13f the PMOS is having 2f

could anybody give idea on this why NMOS and NMOS in NWELL caps are good to use as D-CAPs

apart from this it would be much appreciable if anybody provide or point me docs on NMOS in NWELL how it gives better cap w.r.t to NMOS cap ?


Thanks for your support

Kumar

NMOS in NWELL? is it Deep NWELL?
 

kumar123

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Hi

Actually i was asking about PMOS compared to NMOS in NWELL and simple NMOS cap .

IS there any difference between NWELL CAP and DEEP NWELL cap ?

Kumar
 

funster

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NMOS has lower channel resistance thyan PMOS with sam W/L ratio.

that's good for decouple use.

best regards




kumar123 said:
Hi ,

Can anyone has an idea why PMOS canot be used as a CAP?
when i did rough simulation taking PMOS and NMOS of same L and Wp= 2*Wn i found that PMOS is giving more CAP value say if NMOS has value 0.13f the PMOS is having 2f

could anybody give idea on this why NMOS and NMOS in NWELL caps are good to use as D-CAPs

apart from this it would be much appreciable if anybody provide or point me docs on NMOS in NWELL how it gives better cap w.r.t to NMOS cap ?


Thanks for your support

Kumar
 

alias0823

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Excuse me
Why channel resistance would influence decouple use?
thanks

funster said:
NMOS has lower channel resistance thyan PMOS with sam W/L ratio.

that's good for decouple use.

best regards




kumar123 said:
Hi ,

Can anyone has an idea why PMOS canot be used as a CAP?
when i did rough simulation taking PMOS and NMOS of same L and Wp= 2*Wn i found that PMOS is giving more CAP value say if NMOS has value 0.13f the PMOS is having 2f

could anybody give idea on this why NMOS and NMOS in NWELL caps are good to use as D-CAPs

apart from this it would be much appreciable if anybody provide or point me docs on NMOS in NWELL how it gives better cap w.r.t to NMOS cap ?


Thanks for your support

Kumar
 

leeenghan

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Hi,

The channel has resistance. PMOS is holes and NMOS is electron, so PMOS channel resistance is much higher than NMOS.

So, the cap can be modelled by a resistance in series to a CAP. If the resistance is big, the response of the cap is slower, and this is bad for decoupling. Run a simulation (not looking at the cap vaule) and you can see the big different.

Regards,
Eng Han
 

jcpu

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PMOS can be used as cap.
only associated Nwell has to be tied to some VDD.
Try to keep MOST in inversion region,
capacitance should be he oxide capcitance.

Have fun,
 

A.Anand Srinivasan

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can somebody explain about the decoupling that is being talked about.... i havn't heard anything about this and would like to know...
 

kumar123

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Hi eng han,


Hi i agree with you that NMOS channel resisstance is less compared to PMOS
but to be act as a DE-CAP one would be tying source,drain and bulk together to VSS and gate to VDD in that aspect the resistance exist between source and drain must be like a shorted so no need to consider it .please feel free to correct me if i am wrong fron this DE-CAP perspective.

probably what you may pointing is the substrate resistance btween gate to substrate terminals stood as series resistance

hi jcpu,
i have few words on your comment if i am going to use PMOS as cap definitely gate is one terminal(given to VSS along with substrate(p-type) connected) and source ,drain and NWELL are tied to VDD
so it definitely operate in inversion region am i wrong?

apart from theory i have done some simulations in SPICE on this and found results bit confusing

.PRINT all(C)

when i used above statement to print all junction capacitances i found Cgs always be at 0 and Cbd=Cbs =total capacitance between terminals X(gate) (swept from
-VCC to 2*VCC) and Y(source,drain,bulk shorted together) (always tied to VSS)
Cgd is varying according to region of operation , Cds always has neglegible value

Any suggestins would be appreciable on this


From the PMOS point of view cap is formed between terminal X( gate and P-substrate tied to VSS ) terminal Y( source, drain and NWELL connected together given to VCC) when i did simulation i found 10X more cap than an normal NMOS realized cap , i was wondering what is the concept behind this to happen.

Regards
Kiran
 

pixel

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I have used pmos like previously described bulk + sorce + drain connected to vdd.
It achieves good capacitance per unit area, and can be used when is no need for acurate capacitor value i.e decoupling, or dummy circuit voltage stabilization and noise cutt-off ...
 

leeenghan

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Hi Kumar,

The resistance is the channel resistance, and not the resistance you are referring to. Please imagine there are many small resistors in series in the channel (i.e. in the area under the poly). As the mobility of the holes are slower than electrons, the charging and discharging are slower.

When performing the simulation, study the transient response (e.g. you can hook-up an RC circult, and see if NMOS or PMOS and see which one is more capacitive, and has faster response for charging and discharging.

Regards,
Eng Han
 

laglead

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NMOS has more bandwidth than PMOS cap.
 

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