Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In big and complex project you'll have to menage a lot of different clock domain so the necessity of a lot of PLL is normal, more the FPGA are bigger more things you'll integrate in a single chip.
Doing things that you do on 2 different boards often can be condensed in only one board with a bigger FPGA with an obvious reduction of costs and better integrations.
I don't know why they are at boundary of FPGA but to me seems that it could be because PLL are a different topology of circuit than all the part of FPGA and to fabs maybe it's simpler put it at boundary so with the changing size of the FPGA your layout still be more or less the same.
Moreover clock out of a PLL usually go on a global line and is used by a lot of FPGA and so you could put it at center or boundaries, the choice is imo driven by layout.
Mine are most of all supposition but maybe I've taken some points
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
