[SOLVED] Why par report a clock "NOT completely routed"?

[hfly47]

The part of FPGA is V6-XC6VLX760-1, which has 18 clock regions. That clock drives logic in 9 clock regions, and I don't know whether this is the root cause.
And:
1. The number of utilized BUFG is 18, smaller than 32.
2. The number of global clocks in each clock region is smaller than 12.

Thanks a lot.

 

[hfly47]

Thanks for your attention, I have find the root cause with FPGA Editor.