Re: Why?
From "The Art Of Analog Layout" by Hastings
"In an N-well CMOS process, such as that illustrated in Figure 3.21, NMOS transistors occupy the epi, and PMOS transistors reside in the well. The increased total dopant concentration caused by counterdoping the well slightly degrades the mobility of majority carriers within it. The N-well process therefore optimizes the performance of the NMOS transistor at the expense of the PMOS transistor. As a side effect, the N-well process also produces the grounded substrate favored by most circuit designers.
A P-well CMOS process uses an N+ substrate, an N-epitaxial layer, and a P-well.
NMOS transistors are formed in the P-well and PMOS transistors in the epi. This
process optimizes the PMOS transistor at the expense of the NMOS transistor, but
the NMOS still outperforms its counterpart because electrons are more mobile than
holes. A P-well process requires that the substrate connect to the highest-voltage
supply instead of ground. Designs that employ multiple power supplies often have
difficulty biasing an N-type substrate because of ambiguities in the sequencing of
the supplies.
Both P-well and N-well CMOS processes exist.The N-well process offers a slightly
better NMOS transistor, and it allows the use of a grounded substrate. N-well
CMOS is also upwardly compatible with BiCMOS technology, as will become
apparent later in this chapter.The N-well process has therefore been chosen to illustrate CMOS technology."
