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Why not use thick metal enclosure for heatsinking FETs?

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cupoftea

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Hi,

We have a PCB to bring up from a customer (their engineer left)
It’s a 300W Synchronous Pushpull, 24vin, 32vout, each Pri FET switches at 153kHz.
Transformer is planar and 1:2 (pri:sec)

The Pri FETs are SMD as follows…
https://www.infineon.com/dgdl/Infin...N.pdf?fileId=5546d4627617cd8301762e04616a61b8

The Sec Sync FETs are SMD as follows…
https://www.infineon.com/dgdl/Infin...N.pdf?fileId=5546d46277921c320177aa5221467dea

The PCB is enclosed in a thick walled aluminium enclosure on all 6 sides. Walls are some 1cm thick all round.
However, bizarrely, neither primary FETs, nor secondary Synch FETs, are actually directly heatsunk to this enclosure. Both Pri and sec side FETs are actually mounted on the underside of the PCB, and via “gouges” in the bottom aluminium, they get gap-padded via their top surface to the bottom of the alu enclosure. (the "gouges" being needed because the FETs obviously stick out from the bottom surface of the PCB)

As you know, the Gap pad forms a relatively poor thermal pathway from FET tops to alu base.

{Incidentally, the Planar transformer woudl also be gap-padded to the enclosure base...there is a cutout in the PCB for it.

It’s a 4 layer board and the pri fets have thermal vias to top copper, and these thermal vias traverse copper pours on all 4 planes.
The secondary FETs have no thermal vias, but there is copper planes on all 4 layers “above” it. On the top layer, directly above the secondary FETs, lies an SMD inductor dissipating 3W (IHLP8787)

Why have they not gone the “standard” route and had top mounted SMD FETs, with thermal vias to bottom copper, then 6um thick thermal/insulation pad to the thick metal enclosure base?
I am thinking the only reason would be fear of common mode emissions, but if that scares them, then why is there no input common mode choke?

So , Can you think of a reason for not making best use of the thick aluminium enclosure for heatsinking these 4 FETs?
 

Hi, Sorry for long post above.
For Brevity....
What's wrong with heatsinking SMPS SMD FETs by having them on a PCB, with thermal vias going through to bottom copper pour...then 0.05mm thin thermal/insulator pad....then that PCB screwed to a metal heatsink/plate?

...Why instead, do people put the SMD FETs on the bottom side of the PCB, then gouge out a divet in the metal plate for the said FETs, then gap-pad the SMD FET tops to the metal plate?
 
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Thickness helps only lateral conduction, you want a short
straight path to the coolness. Now 1cm might give you some
lateral conduction but I'd be trying to calculate that (though
an "end fed slab with convection" (as the half-case for center
mounted heaters) is probably multiphysics FEA territory.

Or you could instrument it up at full load minimum spec
airflow, for the cost of 2 thermocouples and some 5-min
epoxy (or thermal paste & clamp). Make it three, one on
the hardest-stressed power device case?
 
Thankyou, regarding the central question here, apologies for long winded first post.....please may i restate...

You have a 1cm thick metal plate/heatsink, onto which you will mount your 300W SMPS PCB, (24vin, 32vout, 153kHz pushpull) which comprises SMD Power FETs.
Would you prefer to mount your SMD FETs to the top of the PCB, or the bottom, and why?
Which way could give best thermal conduction to heatsink plate?

At the risk of snowing the issue, please answer separately for the case of SMD FETs with metal heat tab on the top surface, and bottom surface?

N.B.
Here is an example of an SMD FET with heat tab on top surface
IAUS260N10S5N019T

...long ago, in a company, we decided that SMD FETs with top heat tabs were bad news.....from complexity of heatsinking arrangement needed, as well as there rarity and nil-stock-likeliness?

'top-heat-tab' SMD FETs are rare, and there is no way of searching for them on any search site, not even digikey.
 
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I would imagine that top heat slab would carry a lot of TCE mismatch issues in the stack. There has to be some "soft yet durable" element to take up strain / stress but then this starts to add inductance if it turns into a harness or layout compromises....
 
Thanks, yes i tend to agree.
I mean, if you have a 1cm think aluminium heatsink plate to mount an SMD SMPS PCB on, and you dont use top layer SMD FETs, (with heat tabs on their back side) thermal via'd through to that heatsink, then i can't understand why not?
...in that situation putting the SMD FETs on the bottom side of the PCB appears not to make any sense whatsoever?
 

i did not follow all of the discussion, and my apologies if i missed something:

the junction to ambient thermal resistance of the primary FETs (IAUS260N)
is 2.8 K/W out the top and 40K/W out the bottom (through the PCB)

mounting the FET on the bottom of the PCB and putting the aluminum heat sink in contact with the top of the FET
is the same as mounting the FET on the top of the PCB and putting the aluminum heat sink in contact with the top

mostly, surface mount parts on the top or bottom behave the same
one "merely" aligns the low thermal resistance between the source and the cold
reads like that's what your customer did
 
is the same as mounting the FET on the top of the PCB and putting the aluminum heat sink in contact with the top
..thanks, though in most cases, AYK, the heatsink is below....eg the base of the enclosure. The base is "there anyway", so it seems to make sense to use it......as such, the "back-tab" fets seem far better.

the junction to ambient thermal resistance of the primary FETs (IAUS260N)
is 2.8 K/W out the top and 40K/W out the bottom (through the PCB)
Thanks...It would be great to know the thermal resistance going through 4 layer pcb with planes and thermal vias (vias in pads plated over)
--- Updated ---

Surely using SMD FETs with top heat tabs, and then mounting them on the PCB bottom, and then having to gouge out the alu enclosure base like in the attached is madness?...way too expensive?
(the fets with "top-tabs" are gap padded to the alu enclosure, in the "Gouge")
 

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