Hi,all
i'd like to inquire about why Vc1 (the terminal at the output of opamp ) need no compensation ,since the output of opamp links to the the gate of the PMOS,that is two stage opamp, i think it should add compensation.
anyone could help, thx a lot
I am almost positive since they are drawing the amplifier as just a symbol, they are probably assuming the amp is unity gain stable. The compensation for this circuit would be in the amplifier stage.
R3 is to match the drain voltage of M3 to M2 that could be interpreted as compensation. The loop outside the opamp will have poles. So compensation is strongly suggest. The cap load at the bandgap output is the first pole. The second is the input cap of the kT amplifier. The third is the gate cap load at the output of the opamp.
Why there is a believe based on the circuit topology not to investigate stability?!
Yes, I agree with rfsystem. Circuit has two loops -positive and negative. WIth capacitive load at the output of you bandgap, probably you will get unstable conditions. Because loop gain Vc1 - Vo - V+ have changed
This kind of Brokaw-cell bandgap is very interesting... I always wonder how you compensate the overall circuit effectively. Where do you add the compensation capacitor and how small could the capacitor be?
There is a negative loop and a positive loop, with the negative loop gain much larger than the positive one. But compensation is still necessary to ensure close-loop-stability.
Anyone could shed more lights on this matter? Thanks in advance.