Why net (wire) delays are zero after synthesize?

[asicguygmail]

Hi,
I synthesize an RTL code with Synopsis. I add a wire_load_model to my synthesize process. At the end I do a report_timing and I see all gate delays but I don't see any net (wire) delays in the timing paths.

This is the command that I use to add wireloadmodel:

set current_design cnode
set_wire_load_model -name "TSMC8K_Lowk_Aggresive"

Why there is no delay associated with wires between gates?
Do the gate (cell) delays include the wire delays or they will show up after place and route and the delays that I see must be mutiplied by a factor bigger than 1?
Following commands didn't help neither and I still don't see wire (net) delays:

set auto_wire_load_selection true
set_wire_load_mode enclosed

Thanks for any help and feedback
Dave

 

[asic_service]

It's usually the delay of wires are very small. And the delay numbers reported by DC just has 0.01ns precise, by default. Then the wire delay will be shown as 0.00 (0.0001 -> 0.00)
You may see the delays by:
1): Write a special RTL code, make one wire has a lot of load. --> 2): change the number precise reported by DC (by one DC variable) --> 3): maybe also need the report_timing option (-net)

Thanks.

 

[mail4idle2]

The reason why there is no delay of wires between gates is because synthesis does not know how far they are.

 

[alexhugo]

That might be true but wire_load_model is used for this purpose. What is the point of using wireloadmodels if synthesizer is going to assume zero delays for the nets?

 

[asicguygmail]

Thanks for the info.
I have a huge design in which, we can not ignore net delays since the module is big and I use the biggest wire load model. Should I still get zero wire delays?
Is there anything I can do to more realistic delays? The main problem in this design is wire delays and I want to work on those.
Thanks Again
Dave

 

[OhaAmo]

I think that at this stage the wire load is estimated and treated as capacitance which "connects" to the next gate's capacitance.
You can try varying the wire load and see if you sense changes in the timing for some path. If you see that after putting wire load the path is slower (though the wire delay is 0) you probably can assume that the wire delay is joined to the next gate.

As mail4idle2 said, after synthesis there is no actual wire delay because you don't know how the tool will connect the wires physically.