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The mobility of holes is lesser than that of electrons. Inorder to make the rise and fall times of a gates equal usually the width of PMOS xtor is made higher. So the resistance of it would be less and can attain equal rise and fall times.
In NAND gates the PMOS xtors are connected in parallel and there by its effective resistance decreases. So now one can achieve the same rise and fall times at lower widths of the PMOS. Inaddition you are reducing the cell height also.
it is basically two different capacitances during the switching.... because for each there will be two parallel MOS in one case and one MOS in the other case.... so for the two MOS in parallel case of switching the capacitance will be high....
Consider you have basic inverter which have equal rise and fall time and its Aspect ratio is 2:1. So for symmetric NOR gate with both NMOS have ratio W/L each, you should have both PMOS with aspect ratio four times that of NMOS, i.e., 4W/L each.
But in NAND you can have symmetric rise and fall times with all NMOS and PMOS having aspect ratio W/L each. This is the reason why NAND are preferred over NOR gates..
((NMOS have lesser resistance than PMOS approximately half, so resistance of two NMOS devices (in series) will be equal to one PMOS device on Pull-up side...))
NAND gates is more preferred than NOR gates because of sizing.
NAND is NMOS in series and PMOS in parallel, while NOR is the other way around.
As people have already mentioned, the mobility of hole is less than that of the electron. Therefore, to achieve the same delay (current capability), PMOS needs to be approximately 3 times than NMOS (0.18um technology).
I am not sure if you have taken any digital IC course before, but in essence when you do the transistor sizing any transistor in series need to be sized up more (depending on the number of transistors in series). Therefore, we want to avoid PMOS transistors in series (because they take up more space than NMOS in series at same delay).
That is why NAND is a better choice than NOR.
Added after 43 seconds:
pichuang said:
NAND gates is more preferred than NOR gates because of sizing.
NAND is NMOS in series and PMOS in parallel, while NOR is the other way around.
As people have already mentioned, the mobility of hole is less than that of the electron. Therefore, to achieve the same delay (current capability), PMOS needs to be approximately 3 times bigger than NMOS (0.18um technology).
I am not sure if you have taken any digital IC course before, but in essence when you do the transistor sizing any transistor in series need to be sized up more (depending on the number of transistors in series). Therefore, we want to avoid PMOS transistors in series (because they take up more space than NMOS in series at same delay).
It is not the issue of why dig circuit uses 0->1 or so....it is only for analysis purpose used by designer....basically dischargin of load capacitance is done by many path...the response of CMOS circuit depends on how fast and good u r able to charge load capacitance which happens only at 0->1 transition thru only single path ....supply to output path....
For Nand PMOS are in parallel whereas in case of NOR PMOS is in serial. As u know the mobility of hole is less than the mobility of electron, time taken to switching from ACTIVE state to Saturation state is higher. Same for reverse condition.
So NOR has delay while switching from one state to another state so prefered to use NAND over NOR
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