i have developed my FPGA board using EP1C3T100(CYCLONE) .I use "AS+JTAG"
configration model,but! when i config my FPGA using JTAG ,the log show"can't access JTAG chain".when i using "AS" model ,it can programe EPCS1 chip, but the verifcation is wrong.i have example my board several times. but i can find why?
Perhaps there is a design failure in the schematic. Did you connected all like Altera is doing in there configuration schemes? Did you checked the power supply on each pin of the FPGA?
yes! i have designed the fpga board strictly following the cyclone datasheet.i have also refered to cyclone DSK schematic.the download cable "byteblaster2" which i have bought from market i think may have no problem.The fpga EP1C3t100 's power supply is OK,when i using "AS" mode, the FPGA can generate "DCLK" clock,i can view the clock generated by FPGA in oscillograph.when i power up the FPGA,the "nstatus" ping can give a high status"1".
that means the FPGA reset correctly.but i can't solve the problem.
Do you have the possibility to check your ByteBlaster II cable? I have made the experience that the cable doesn’t work with some notebooks. Did you checked all the wire on the board and of the cable for a proper connection?
1) Check your BB2 with another board, which is exactly working.
2) Try to configure your chip using another configuration scheme. I advice you JTAG configuration. Anyway, it would be easier and sooner to solder a couple of wires then to make own BB2.
I think you should modify the programmer.
Try adding a small capacitor (100p - 470p) between the input of the TCK signal
buffer and the GND. It usually helps.
It is easier to build up a ByteBlaster MV than a ByteBlaster II. The BB MV can be done on a breadboard. Don’t you have the possibility to check your BB II with a working PCB in your company/university/friends?
thanks all! Now i have sovle my problem,i adding a small capacitor (220p) between the input of the TCK signal
buffer and the GND,and then the FPGA works very good.