peleda
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#2
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FvM said:Number four.
linkfox said:FvM said:Number four.
if input is sampled at the posedge, and the transition condition is "in/out", shoud be #4
can anybody explain why #2?
kvingle said:Assuming state(a) is reset state
clock --------- x ----next state -- output(after clock to out delay)
1st posedge 0 stage a 0
2nd posedge 1 stage b 0
3rd posedge 1 stage b 0
4rthposedge 0 stage c 0
5th posedge 1 stage d 0
6th posedge 0 stage c 0
7 posedge 0 stage a 0
8 posedge 1 stage b 0
9 posedge 0 stage c 0
10 posedge 1 stage d 0
11 posedge 1 stage c 1
So #4 is the answer.
thank U friend.if i see it in my exam i'll answer as U saied;kvingle said:Friend.....why are you introducing glitches by your own.. :|
They have given you the input W/F. and thats free of glitches....
as far as the context of this question ans is #4 .........
....period.