why moore is safer then mealy?

[peleda]

#2

 

[linkfox]

Number four.

if input is sampled at the posedge, and the transition condition is "in/out", shoud be #4

can anybody explain why #2?

 

[soloktanjung]

hi,

i'm confused with the output. i think should be number 4 because the output in depend on the posedge clk + current state.

regards

 

[milligator]

Number four.

if input is sampled at the posedge, and the transition condition is "in/out", shoud be #4

can anybody explain why #2?

thank u all
as i know mealy's out put can change with the change of asynchronus input(x)
i think if we connect the output to a register the #4 is correct
else
#2 is correct.

before the 5th clock we are in C state.
and in=1 out=0
in the 5th clock the input=1 and the state changes to D and we see in=1.
and in D because the input is 1 out changes to 1 .
within clock 5 and 6 the input changes to 0 and then out=0;

before the 11th clock we are in C state.
and in=1 out=0
in the 11th clock the input=1 and the state changes to D and we see input is 1
and in D because the input is 1 out changes to 1 .
in 12th clock the input is 1 and then the state changes to B and out=0;

then #2 is correct

i do not know what to Do?!!!!!!!!!

 

[kvingle]

Assuming state(a) is reset state


clock --------- x ----next state -- output(after clock to out delay)
1st posedge 0 stage a 0
2nd posedge 1 stage b 0
3rd posedge 1 stage b 0
4rthposedge 0 stage c 0
5th posedge 1 stage d 0
6th posedge 0 stage c 0
7 posedge 0 stage a 0
8 posedge 1 stage b 0
9 posedge 0 stage c 0
10 posedge 1 stage d 0
11 posedge 1 stage b 1


So #4 is the answer.

 

[milligator]

Assuming state(a) is reset state


clock --------- x ----next state -- output(after clock to out delay)
1st posedge 0 stage a 0
2nd posedge 1 stage b 0
3rd posedge 1 stage b 0
4rthposedge 0 stage c 0
5th posedge 1 stage d 0
6th posedge 0 stage c 0
7 posedge 0 stage a 0
8 posedge 1 stage b 0
9 posedge 0 stage c 0
10 posedge 1 stage d 0
11 posedge 1 stage c 1


So #4 is the answer.

i have drew something wrong.
state D with 1/1 goes to state B. sorry. but nothing changes;
some thing is not clear sor me.
i think without Glitches #4.
#2 is with Glitches.

am I right?:?:
see w w w.seas.upenn.edu/~ese201/abel/abelMealy.html

if we don't use Glitches then it will be like moore.

 

[kvingle]

Friend.....why are you introducing glitches by your own.. :|
They have given you the input W/F. and thats free of glitches....
as far as the context of this question ans is #4 .........



....period.

 

[madhavisai]

moore is less error prone bcoz output depends only on current state so it is glitch free

 

[milligator]

Friend.....why are you introducing glitches by your own.. :|
They have given you the input W/F. and thats free of glitches....
as far as the context of this question ans is #4 .........



....period.

thank U friend.if i see it in my exam i'll answer as U saied;
but i ask u something that is wrong with me.
what happens to out put if we disable the clock?
as i understand the output will not cange in mealy diagrams until the clock pulse edge;

i knew the answer is #4. but some one told me "because mealy is asynchronus the out put can change whenever the input changes"when i checked i saw #2 is correct.i think he made me confuse

 

[ramz]

moore is glitch free... where as meelay is sensitive to glitches