Mar 18, 2008 #1 R reninroy Junior Member level 1 Joined Feb 26, 2008 Messages 18 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,389 why latches are inferred because of the incomplete if else statement..? thanks in advance....
Mar 18, 2008 #2 K kvingle Full Member level 5 Joined Nov 5, 2007 Messages 244 Helped 33 Reputation 66 Reaction score 12 Trophy points 1,298 Location India. Activity points 2,574 Re: verilog unless you don't specify all the cases it is assumed (by synthesis tool) that you don't want to change the output values for cases other than the specified ones.Hence the values would be latched....thats why it (synthesis tool )infers latches
Re: verilog unless you don't specify all the cases it is assumed (by synthesis tool) that you don't want to change the output values for cases other than the specified ones.Hence the values would be latched....thats why it (synthesis tool )infers latches