Why is latch undesirable the most

[jaydip]

Hello,

Why is latch so much undesirable ?? One reason which I keep on listening is, Timing analysis is difficult for latch. But anybody knows why is Timing Analysis difficult for latch? what are the pros and cons of flop vs Latch based designs ?? Are there any more serious reason behind not using latch other than tool's inability to perform timing analysis ??


Thanks

 

[ljxpjpjljx]

latch is level sensitive , register is edge sensitive, so STA is difficult for latch!

 

[jagz]

one reason i know is that since latch is level sensitive, the output could come at any point of the particular level. Hence it could lead to the formation of glitches.

 

[Yury Terentiev]

Hi! Any commercial STA tool will handle latch-based design properly. I'm sure that "timing analysis" which gets harder actually refers to RTL fixes. If one wants to fix a latch based design timing by better balancing the logic among the pipe stages he might have to do a more complex analysis than required for a flop based design.

 

[jaydip]

@Yury Terentiev
Did not quite really get you .. any better explanation ???