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# why input resistance at terminal +and- is low?(used in LDO)

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#### lxcpku

##### Junior Member level 3
Papers from JSSC says input resistance at terminal + and - is low ,i donot quite understand why ? and i think the input resistance depends on the current through the transistor,since it is diode. However , this ciruit is used in LDO,so the current should not be too large,for example:1uA below),then the input resistance at terminal is still low? and why ? could anybody give me exact expression of input resistance at terminal + or - ? thx a lot for your sincere help

btw:what magnitude of this input resistance? like 100k or 1k and so forth,since the pole at this terminal may affect circuit stability, i have to know the probable value of the input resistance

anyone could help me ? thx a lot

Re: why input resistance at terminal +and- is low?(used in L

source terminal basically is a low impedance node.

Re: why input resistance at terminal +and- is low?(used in L

taofeng said:
source terminal basically is a low impedance node.
could u give me more details ? thx

Re: why input resistance at terminal +and- is low?(used in L

because + and - terminal are connected to source node which is low impedance.
this is why this paper does not have any problem on the stability since the output of the LDO is low impedance (+ terminal), which is beyond UGF.

Re: why input resistance at terminal +and- is low?(used in L

taofeng said:
because + and - terminal are connected to source node which is low impedance.
this is why this paper does not have any problem on the stability since the output of the LDO is low impedance (+ terminal), which is beyond UGF.

i still do not understand why source is sure to be low impedance,as it series with the current sink below. and if it is low impedance,could u tell me the probable magnitude?

Re: why input resistance at terminal +and- is low?(used in L

1/gm if not mistake.

I guess the Iq=1uA means all the bias currents ? I am not sure.

Re: why input resistance at terminal +and- is low?(used in L

taofeng said:
1/gm if not mistake.

I guess the Iq=1uA means all the bias currents ? I am not sure.

if iq=1uA,gm=10u(if Vdsat=0.2v),then Rin=1/gm=100k,that is pretty large. not to say iq should be 1uA below .
so why should we think terminal at + or - is low impedance ?

Re: why input resistance at terminal +and- is low?(used in L

Let's put it this way:
1. It is a relatively low impedance compared with the output of the push pull stage(~ M ohm).
2. Just imaging a normal voltage regulator design(without any large capacitor at the output), the output is a high impedance node. And the worst case is when the current is extremely low, by which I mean it is the worst case for stability. This leaves two high impedance nodes, which is potentially unstable. When the current increases, the equivalent load resistance decreases and the output node is pushed to higher frequency, so the phase margin improves.
3. With the + terminal connected to output of regulator. As you calculated, even in 1uA conditions, the impedance is still ten times low than the output node of push-pull stage. It helps for the stability.

Re: why input resistance at terminal +and- is low?(used in L

taofeng said:
Let's put it this way:
1. It is a relatively low impedance compared with the output of the push pull stage(~ M ohm).
2. Just imaging a normal voltage regulator design(without any large capacitor at the output), the output is a high impedance node. And the worst case is when the current is extremely low, by which I mean it is the worst case for stability. This leaves two high impedance nodes, which is potentially unstable. When the current increases, the equivalent load resistance decreases and the output node is pushed to higher frequency, so the phase margin improves.
3. With the + terminal connected to output of regulator. As you calculated, even in 1uA conditions, the impedance is still ten times low than the output node of push-pull stage. It helps for the stability.

oh , i got your explaination .thx a lot for ur sincere help
but in my structure,if Rin=100k (when iq=1uA)and Cload=100pf, BW=1/[(2pi)RC]=16k,is that enough for normal appicaion of LDO ? maybe iq should be even smaller than 1ua,then BW will be less ?

BTW:in the normal application of LDO,what magnitude should be the bandwidth ? some advice ?

i run a simulation, and results shows it is a low impendance pole for sure. and it will not affect the circuit stability. but by hand calculation. the impedance at this terminal is 1/gm, which is over 100K, and fd=1/2pi*RC,which is far smaller than the simulation results. anything wrong with my calculation ?
anybody could help ?suggestions and advice will always be welcom.thx a lot

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