ldhung
Member level 3
When I synthesize the code in Design Compiler,
input matchen;
input conditions;
input [NUM_WORDS-1:0] ss1, ss2, ss3;
output reg [NUM_WORDS-1:0] match_onehot_addr;
always @(matchen)
begin
if (conditions)
match_onehot_addr <= ss1 & ss2;
else
match_onehot_addr <= (ss1 & ss2 & ss3);
end
I have encountered a problem: In design 'machand', port 'matchen' is not connected to any nets. Do you know why ?
Thanks in advance
input matchen;
input conditions;
input [NUM_WORDS-1:0] ss1, ss2, ss3;
output reg [NUM_WORDS-1:0] match_onehot_addr;
always @(matchen)
begin
if (conditions)
match_onehot_addr <= ss1 & ss2;
else
match_onehot_addr <= (ss1 & ss2 & ss3);
end
I have encountered a problem: In design 'machand', port 'matchen' is not connected to any nets. Do you know why ?
Thanks in advance