why input in @always not synthesizable

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ldhung

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When I synthesize the code in Design Compiler,

input matchen;
input conditions;
input [NUM_WORDS-1:0] ss1, ss2, ss3;
output reg [NUM_WORDS-1:0] match_onehot_addr;

always @(matchen)
begin
if (conditions)
match_onehot_addr <= ss1 & ss2;
else
match_onehot_addr <= (ss1 & ss2 & ss3);
end

I have encountered a problem: In design 'machand', port 'matchen' is not connected to any nets. Do you know why ?
Thanks in advance
 

although matchen is inside the sensitive list, no signal inside the always block read it.
In hardware, it is either positive enable or negative enable.
You can make it work by two ways:
1. use matchen as a clock
So write as "always @(posedge matchen)"
2. assuming it is a positive enable
Add line "if(matchen)" before "if(conditions)", but in this case, ss1, ss2, ss3, conditions should be inside the sensitive list.
 

only the process (in verilog) that would implement a flop, does not need to appears inside the process.
if you want to use marchen as "clock", you must declare as "posedge matchen", and "posedge condition" to be use as reset active high
 

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