architecture behavioural of controlunit is
...
type mnemonic is (ADD, MOV, SUB, LOAD, MUL, ANDD, NEG);
signal m : mnemonic;
type state_type is (T1, T2, T3);
signal t : state_type;
-- Mnemonic definition
with instruction_in(15 downto 11) select
m <= ADD when "10001",
MOV when "11000",
SUB when "10010",
LOAD when "01000",
MUL when "10101",
ANDD when "10111",
NEG when "11010";
-- 3 State types
67 if (m = LOAD) then
68 t <= T1;
69 elsif (m = MOV or m = NEG) then
70 t <= T2;
71 else
72 t <= T3;
73 end if;
...
end behavioural;
Error (10500): VHDL syntax error at controlunit.vhd(67) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement,
Error (10500): VHDL syntax error at controlunit.vhd(67) near text "then"; expecting "<="
Error (10500): VHDL syntax error at controlunit.vhd(69) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement,
Error (10500): VHDL syntax error at controlunit.vhd(69) near text "then"; expecting "<="
Error (10500): VHDL syntax error at controlunit.vhd(71) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement,
Error (10500): VHDL syntax error at controlunit.vhd(73) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
architecture behavioural of controlunit is
type state is (READ1, READ2, S1, S2, S3, S4);
signal y : state;
signal instruction : std_logic_vector(15 downto 0);
type state_type is (T1, T2, T3);
signal t : state_type;
type mnemonic is (ADD, MOV, SUB, LOAD, MUL, ANDD, NEG);
signal m : mnemonic;
begin
-- Mnemonic definition
with instruction_in(15 downto 11) select
m <= ADD when "10001",
MOV when "11000",
SUB when "10010",
LOAD when "01000",
MUL when "10101",
ANDD when "10111",
NEG when "11010";
-- 3 State types
if (m = LOAD) then
t <= T1;
elsif (m = MOV or m = NEG) then
t <= T2;
else
t <= T3;
end if;
-- State Machine
process(clk, reset)
begin
if (reset = '1') then
instruction <= x"0000";
elsif (clk'event and clk = '1') then
case y is
when READ1 => get_next_inst <= '0';
y <= READ2;
when READ2 => y <= S1;
when S1 => if (t = T1) then
datapath_in <= instruction_in(7 downto 0);
y <= READ1;
else y <= S2;
end if;
when S2 => y <= S3;
when S3 => if (t = T2) then
y <= READ1;
else y <= S4;
end if;
when S4 => y <= READ1;
when others => y <= READ1;
end case;
end if;
end process;
end behavioural;
-- 3 State types
if (m = LOAD) then
t <= T1;
elsif (m = MOV or m = NEG) then
t <= T2;
else
t <= T3;
end if;
-- 3 State types
process(m) is
begin
if (m = LOAD) then
t <= T1;
elsif (m = MOV or m = NEG) then
t <= T2;
else
t <= T3;
end if;
end process;
t <= T1 when m = LOAD else
T2 when (m = MOV) or (m=NEG) else
T3;
process(a,b,c) is
begin
if c = '0' then
d <= a xor b;
else
d <= b xor c;
end if;
end process;
process(clk,gsr) is
begin
if gsr = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
-- 3 State types
if (m = LOAD) then
t <= T1;
elsif (m = MOV or m = NEG) then
t <= T2;
else
t <= T3;
end if;
a <= b xor c when z = '1' else '0';
process(b,c,z) is
begin
if z = '1' then
a <= b xor c;
else
a <= '0';
end if;
end process;
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