From a mathematical point of view it is clear that the equation for hold time is independent of the clock cycle. So a hold violation cannot be fixed by making the clock slower or faster. From an understanding perspective this is because hold problems are caused by the reg-to-reg logic being too fast. It refers to a timing delay calculated between a clock edge arriving at the launching flip-flop and the *same edge* (!!) arriving at the capturing flip-flop.
The setup equation does include the clock period. Setup is the opposite problem where the datapath logic is too slow. You can solve a setup violation by slowing down the clock. The crucial difference is that the setup equation refers to 2 *different edges* of the clock - the capturing edge is one period later that the launching edge. So clock period is germain to setup.
And that is why setup,and not hold, determines fmax.