* PSpice Model Editor - Version 9.2.1
*$
.SUBCKT IXTP02N120P G D S
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*Note: *
* Althought models can be a useful tool in evaluating device *
* performance, they cannot model exact device performance *
* under all conditions, nor are they intended to replace *
* bread boarding for final verification. Therefore IXYS does *
* not assume any liability arsing from their use. IXYS reserves *
* the right to change models without prior notice. The Pspice model *
* does not constitute product data sheet. Designer should refer to *
* the data sheet to guranteed the limit and specification. *
*********************************************************************
** model generated on August 31, 2012
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M110 D G S1 S1 MM111
L_s S S1 1n
.MODEL MM111 NMOS
+ LEVEL=3
+ L=2.0000E-6
+ W=.33
+ KP=1.0331E-6
+ RS=10.000E-3
+ RD=59.148
+ VTO=2.9879
+ RDS=1.2000E9
+ TOX=2.0000E-6
+ CGSO=191.89E-12
+ CGDO=16.167E-12
+ CBD=191.99E-12
+ MJ=1.4624
+ PB=1.5310
+ RG=10.000E-3
+ RB=1.0000E-3
+ GAMMA=0
+ KAPPA=0
*
L_bd S2 S 1n
D_1 S2 D BD
.MODEL BD D
+ IS=3.0108E-16
+ N=2.7849
+ RS=1.0000E-3
+ CJO=1.0000E-12
+ M=.3333
+ VJ=.75
+ ISR=10.010E-21
+ BV=1.1999E3
+ IBV=25.890E-3
+ TT=28.793E-6
.ENDS
*$